The present invention relates to the field of electronic interconnection structures and IC packaging technology.
Current integrated circuit (IC) chip packaging technologies commonly rely on an interconnection substrate containing circuitry to serve as an interconnection base. The interconnection base redistributes the I/O (input/output) terminals or external terminals of the IC to a more optimized contact spacing for making an interconnection between I/O terminals or external terminals of the other parts of assembly. An example of the assembly is when the IC package is mounted on and interconnected to a printed circuit board (PCB). The interconnection between the IC chip or die and the chosen package is normally accomplished using wire bonding, which connects the chip terminals to terminals on the package by thin wires. Alternatively, the chip terminals are interconnected to the IC package substrate by means of metal bumps, solder balls or conductive adhesives. Also, several stacked chips within an IC package may be provided.
The I/O terminals of the IC package are located in various manners depending on the IC package design. For area array type IC packages, the I/O contact terminals are located all on one surface of the IC package. In some IC package designs the contacts are disposed in a manner that facilitates stacking of packages, possibly with through access from the bottom to the top surface for area array type packages, for accomplishing a package-on-package (POP) structured semiconductor device. One special case is for stacking a memory IC with an ASIC IC (Application Specific Integrated Circuit) to increase PCB density. In such area array IC packages the external terminals may be provided with a common land or terminal that can be accessed from both the top and the bottom.
POP type semiconductor devices exist currently on the market with different package dimensions. However, optimized high frequency and high bus width interfaces for POP devices have not been available. Present day POP devices provide support for only one mass memory interface (Flash memory) and a low frequency, 16-bit DDR SDRAM memory (Double Data Rate Synchronous Dynamic Random Access Memory). SDRAM is a type of DRAM memory that can run at higher clock speeds than conventional memory. Flash memory is a special type of EEPROM memory (Electrically Erasable Programmable Read-only Memory).
There are two major architectures of flash memory: NOR and NAND. NOR applications typically use the memory to store and execute operating system (OS) code. As a result, the NOR products evolved with lower density and higher random access performance compared to NAND flash memory with higher density and faster sequential access. While this meets the application needs, the higher cost-per-bit compared to the NAND products makes it an inappropriate choice as a storage media. The applications for NAND flash memory evolved later, as the demand for higher density for storage emerged. NAND applications use the memory to store large quantities of information and therefore require much higher density. With the NOR and NAND memories having such distinct characteristics, it should be possible to choose the appropriate one for each application or semiconductor device. In particular, it should be possible to provide the ASIC IC package easily with appropriate flash memory of choice.
Moreover, present day POP devices provide limited mechanical reliability due to the number and location of solder balls supporting the top device of the POP package.